Step 1: the DC bias point
An amplifier first needs a quiet operating point in the middle of the active region, so the signal can swing both ways. A voltage divider R1–R2 holds the base at a fixed voltage, and the emitter resistor RE sets the current: VE = VB − 0.7 V, so IE = VE/RE. Because this hardly depends on β, the bias stays put when the transistor is swapped.
VTH = VCC·R2/(R1 + R2), RTH = R1 ∥ R2 IB = (VTH − VBE) / (RTH + (β + 1)·RE) IC = β·IB, VCE = VCC − IC·RC − IE·RE
Step 2: small-signal gain
For a small signal, the transistor looks like an emitter resistance re = VT/IE in series with whatever emitter resistance the signal sees. The collector current change flows through RC in parallel with the load RL (the coupling capacitors pass the signal but block DC), so the gain is the ratio of the two resistances, with a minus sign: the output is inverted.
re = VT / IE ≈ 25.9 mV / IE Av = −(RC ∥ RL) / (re + RE,ac) Rin = R1 ∥ R2 ∥ (β + 1)(re + RE,ac)
The bypass capacitor
A capacitor CE across RE shorts it for the signal but not for DC. With it (RE,ac = 0) the gain is large, −RC∥RL/re, but depends on re, which changes with current: big signals distort. Without it (RE,ac = RE) the gain falls to about −RC∥RL/RE, but becomes predictable and much more linear. That trade of gain for stability is negative feedback.
Distortion and clipping
The signal moves the operating point along the AC load line. Push too far and it runs into a wall: cutoff, where the collector current reaches zero and the output’s top flattens, or saturation, where VCE reaches about 0.2 V and the bottom flattens. Even before clipping, a bypassed stage distorts, because the collector current is exponential in VBE. Biasing Q in the middle of the AC load line gives the largest clean swing.
Worked example (the simulator’s default values)
- VCC = 12 V, R1 = 100 kΩ, R2 = 22 kΩ, RC = 4.7 kΩ, RE = 1 kΩ, RL = 10 kΩ, β = 100.
- VTH = 12 × 22/122 = 2.16 V, RTH = 18.0 kΩ → IC = 1.26 mA; VB = 1.94 V, VE = 1.28 V, VC = 6.06 V, VCE = 4.79 V.
- re = 25.9 mV/1.28 mA = 20.3 Ω; RC ∥ RL = 3.20 kΩ.
- Bypassed: Av = −3.20 k/20.3 ≈ −156 (43.9 dB). A 2 mV input gives about 0.31 V out.
- Unbypassed: Av = −3.20 k/(20.3 + 1000) ≈ −3.1, and Rin rises from 1.84 kΩ to 15.3 kΩ.
- Bypassed with 10 mV in: the output reaches −1.91 V but only +1.30 V, already visibly distorted; by 50 mV it clips.
Common mistakes
- Forgetting the load. The gain uses RC ∥ RL, not RC alone.
- Including RE in the gain when it is bypassed, or leaving it out when it is not.
- Biasing near one end of the load line. The output then clips on that side long before the other.
Common questions
What is the voltage gain of a common-emitter amplifier?
Av ≈ −(RC ∥ RL)/(re + RE,ac), where re = VT/IE ≈ 26 mV/IE. With the emitter resistor bypassed RE,ac = 0 and the gain is large; unbypassed it is about −RC/RE. The minus sign means the output is inverted.
Why use voltage-divider bias?
It fixes the base voltage and lets the emitter resistor set the current, so the Q-point barely depends on β, which varies from transistor to transistor.
What causes clipping in a transistor amplifier?
The output can only swing until the transistor reaches cutoff (IC = 0) or saturation (VCE ≈ 0.2 V). A signal larger than that has its peaks flattened.